The present invention relates in general to digital logic conversion circuits having metal semiconductor field effect transistor (MESFET) devices and, in particular, to conversion circuits for converting digital signals from emitter coupled logic (ECL) voltage levels to gallium arsenide (GaAs) voltage levels.
As the use of gallium arsenide devices increases in digital logic circuits, there is a need for a method of providing compatible voltage levels between the new gallium arsenide circuits and digital logic circuits used in older forms of circuitry such as ECL. Circuits for converting digital logic ECL signals to digital logic GaAs signals are known in the prior art but usually involve extensive inner relationship of the gallium arsenide devices to the emitter coupled devices and add substantially to the number of components in the logic circuits.
The present invention has the advantage of converting ECL to gallium arsenide signals with a minimum of interconnection between the different types of circuitry and with a minimum number of components. Furthermore, the gallium arsenide circuit offers a substantial amount of immunity to temperature and process variables. There is a further advantage of the present invention in that the conversion circuit may offer a useful amount of switching hysteresis during the conversions, minimizing the effect of random noise on the signal lines.
Although the present invention relates to gallium arsenide devices, the invention can also be used with other semiconductor technologies which support MESFET transistor structures. For example, technologies using InP devices. U.S. Pat. No. 4,150,308 issued to Adlhoch and U.S. Pat. No. 4,375,677 issued to Schuermeyer are representative of prior art in this field. Adlhoch teaches that in silicon IGFET technology it is possible to define circuits containing cross-coupled pairs of both p-channel and n-channel devices to achieve conversion between one set of signal levels and another. Schuermeyer teaches that in digital GaAs MESFET technology it is possible to define a capacitively cross-coupled circuit for dynamic random access memory applications. Other variations of cross-coupled static random access memory circuits can also be found in prior silicon and GaAs art. Nevertheless, what is not appreciated or anticipated by the prior art is a central concept of this invention, viz., the remarkable utility in defining an ECL/GaAs input circuit with a circuit topology having a substantial degree of structural similarity to the GaAs logic on the same die. Specifically, by this technique, not only is it possible to achieve compatibility of signal levels between the input circuit and the logic for a given process, but because of the intentional high degree of structural similarity of the circuits, this compatibility is automatically maintained over a substantially wider range of process and temperature variations than by conventional methods. The maintenance of this compatibility is a significant factor in increasing the overall process yield of the digital GaAs die, thereby producing a significantly more profitable product.